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irs233(0,2)(d)(s&j)pbf 3phasebridge driver product summary description packages the irs233(0,2)(d)(s & j) is a high voltage, high speed power mosfet and igbt driver with three independent high and low side referenced output channels. proprieta ry hvic technology enables ruggedized monolithic construct ion. logic inputs are compatible with cmos or lsttl outp uts, down to 3.3 v logic. a groundreferenced operationa l amplifier provides analog feedback of bridge curren t via an external current sense resistor. a current trip fu nction which terminates all six outputs is also derived from th is resistor. an open drain fault signal indicates if an overcur rent or undervoltage shutdown has occurred. the output driv ers feature a high pulse current buffer stage designed for minimum driver crossconduction. propagation delays are matched to simplify use at high frequencies. the fl oating channel can be used to drive nchannel power mosfet or igbt in the high side configuration which opera tes up to 600 volts. absolute maximum ratings features floating channel designed for bootstrap operation fully operational to +600 v tolerant to negative transient voltage C dv/dt imm une gate drive supply range from 10 v to 20 v undervoltage lockout for all channels overcurrent shutdown turns off all six drivers independent halfbridge drivers matched propagation delay for all channels 3.3 v logic compatible outputs out of phase with inputs crossconduction prevention logic integrated operational amplifier integrated bootstrap diode function (irs233(0,2)d) rohs compliant june 1 2011 irs233(0,2)(d)(s & j)pbf v offset 600v max. i o+/ 200 ma / 420 ma v out 10 v C 20 v (233(0,2)(d)) t on/off (typ.) 500 ns deadtime (typ.) 2.0 us (irs2330(d )) 0.7 us (irs2332(d)) 28lead soic
typical connection applications: *motor control *air conditioners/ washing machines *general purpose inverters * micro/mini inverter drives downloaded from: http:///
irs233(0,2)(d)(s&j)pbf qualification information ? industrial ?? qualification level comments: this family of ics has passed jedecs industrial qualification. irs consumer qualificat ion level is granted by extension of the higher industrial level . soic28w msl3 ??? , 260 c (per ipc/jedec jstd020) moisture sensitivity level plcc44 msl3 ??? , 245 c (per ipc/jedec jstd020) human body model class 2 (per jedec standard jesd22a114) esd machine model class b (per eia/jedec standard eia/jesd22a115) ic latchup test class i, level a (per jesd78) rohs compliant yes ? qualification standards can be found at internation al rectifiers web site http://www.irf.com/ ?? higher qualification ratings may be available shoul d the user have such requirements. please contact your international rectifier sales representative for fu rther information. ??? higher msl ratings may be available for the specifi c package types listed here. please contact your international rectifier sales representative for fu rther information. downloaded from: http:///
irs233(0,2)(d)(s&j)pbf absolute maximum ratings absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. all vo ltage parameters are absolute voltages referenced to v so . the thermal resistance and power dissipation rati ngs are measured under board mounted and still air conditio ns. symbol definition min. max. units v b1,2,3 highside floating supply voltage 0.3 620 v s1,2,3 highside floating offset voltage v b1,2,3 20 v b1,2,3 + 0.3 v ho1,2,3 highside floating output voltage v s1,2,3 0.3 v b1,2,3 + 0.3 v cc lowside and logic fixed supply voltage 0.3 20 v ss logic ground v cc 20 v cc + 0.3 v lo1,2,3 lowside output voltage 0.3 v cc + 0.3 v in _______ ___ ___ logic input voltage ( hin1,2,3, lin1,2,3 & itr ip) v ss 0.3 (v ss + 15) or (v cc + 0.3) whichever is lower v flt fault output voltage v ss 0.3 v cc +0.3 v cao operational amplifier output voltage v ss 0.3 v cc +0.3 v ca operational amplifier inverting input voltage v ss 0.3 v cc +0.3 v dv s /dt allowable offset supply voltage transient 50 v/ns (28 lead soic) 1.6 p d package power dissipation @ ta +25 c (44 lead plcc) 2.0 w (28 lead soic) 78 rth ja thermal resistance, junction to ambient (44 lead plcc) 63 c/w t j junction temperature 150 t s storage temperature 55 150 t l lead temperature (soldering, 10 seconds) 300 c downloaded from: http:///
irs233(0,2)(d)(s&j)pbf recommended operating conditions the input/output logic timing diagram is shown in f igure 1. for proper operation the device should be used within the recommended conditions. all voltage parameters are absolute voltage referenced to v so. the v s offset rating is tested with all supplies biased at 15 v differentia l. note 1: logic operational for v s of (v so 8 v) to (v so +600 v). logic state held for v s of (v so 8 v) to (v so C v bs ) . note 2: operational for transient negative vs of vss 50 v with a 50 ns pulse width. guaranteed by design. r efer to the application information section of this datasheet for more details. note 3: cao input pin is internally clamped with a 5.2 v z ener diode. dynamic electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss , c l = 1000 pf, t a = 25 c unless otherwise specified. symbol definition min typ max units test conditions t on turnon propagation delay 400 500 700 t off turnoff propagation delay 400 500 700 v s1,2,3 = 0 v to 600 v t r turnon rise time 80 125 t f turnoff fall time 35 55 v s1,2,3 = 0 v t itrip itrip to output shutdown propagation delay 400 660 920 t bl itrip blanking time 400 t flt itrip to fault indication delay 350 550 870 t flt, in input filter time (all six inputs) 325 t fltclr lin1,2,3 to fault clear time (2330/2) 5300 8500 13700 1300 2000 3100 dt deadtime: (irs 2330(d)) (irs2332(d)) 500 700 1100 400 mdt deadtime matching: : (irs2330(d )) (irs2332(d)) 140 v in = 0 v & 5 v without external deadtime mt delay matching time (t on , t off ) 50 v in = 0 v & 5 v without external deadtime larger than dt pm pulse width distortion 75 ns pm input 10 s note: for high side pwm, hin pulse width must be > 1.5 usec symbol definition min. max. units v b1,2,3 highside floating supply voltage v s1,2,3 +10 v s1,2,3 +20 v s1,2,3 static highside floating offset voltage v so 8 (note1) 600 v st1,2,3 transient highside floating offset voltage 50 (note2) 600 v ho1,2,3 highside floating output voltage v s1,2,3 v b1,2,3 v cc lowside and logic fixed supply voltage 10 20 v ss logic ground 5 5 v lo1,2,3 lowside output voltage 0 v cc v in logic input voltage (hin1,2,3, lin1,2,3 & itr ip) v ss v ss + 5 v flt fault output voltage v ss v cc v cao operational amplifier output voltage v ss v ss + 5 v ca operational amplifier inverting input voltage v ss v ss + 5 v t a ambient temperature 40 125 c downloaded from: http:///
irs233(0,2)(d)(s&j)pbf dynamic electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss , c l = 1000 pf, t a = 25 c unless otherwise specified. symbol definition min typ max units test conditions sr+ operational amplifier slew rate (+) 5 10 sr operational amplifier slew rate () 2.4 3.2 v/s 1 v input step downloaded from: http:///
irs233(0,2)(d)(s&j)pbf static electrical characteristics v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss and t a = 25 c unless otherwise specified. the v in, v th and i in parameters are referenced to v ss and are applicable to all six logic input leads: hi n1,2,3 & lin1,2,3. the v o and i o parameters are referenced to v so1,2,3 and are applicable to the respective output leads: ho1,2,3 or lo1,2,3. symbol definition min typ max units test conditions v ih logic 0 input voltage (out = lo) 2.2 v il logic 1 input voltage (out = hi) 0.8 v v it,th+ itrip input positive going threshold 400 490 580 v oh high level output voltage, v bias v o 1000 v in = 0 v, i o = 20 ma v ol low level output voltage, v o 400 mv v in = 5 v, i o = 20 ma i lk offset supply leakage current 50 v b = v s = 600 v i qbs quiescent v bs supply current 30 50 a v in = 0 v or 4 v i qcc quiescent v cc supply current 4.0 6.2 ma v in = 4 v i in+ logic 1 input bias current (out =hi) 400 300 100 v in = 0 v i in logic 0 input bias current (out = lo) 300 220 100 v in = 4 v i itrip+ high itrip bias current 5 10 a itrip = 4 v i itrip low itrip bias current 30 na itrip = 0 v v bsuv+ v bs supply undervoltage positive going threshold 7.5 8.35 9.2 v bsuv v bs supply undervoltage negative going threshold 7.1 7.95 8.8 v ccuv+ v cc supply undervoltage positive going threshold 8.3 9 9.7 v ccuv v cc supply undervoltage negative going threshold 8 8.7 9.4 v ccuvh hysteresis 0.3 v bsuvh hysteresis 0.4 v r on, flt fault low onresistance 55 75 i o+ output high short circuit pulsed current 250 180 v o = 0 v, v in = 0 v pw 10 us i o output low short circuit pulsed current 420 500 ma v o = 15 v, v in = 5 v pw 10 us r bs integrated bootstrap diode resistance 200 v os operational amplifier input offset voltage 20 mv v so = 0.2 v i ca ca input bias current 100 na v ca = 1 v cmrr operational amplifier common mode rejection ratio 80 v so = 0.1 v & 5 v psrr operational amplifier power supply rejection ratio 75 db v so = 0.2 v v cc = 9.7 v & 20 v v oh,amp operational amplifier high level output voltage 4.8 5.2 5.6 v v ca = 0 v, v so =1 v v ol,amp operational amplifier low level output voltage 40 mv v ca = 1 v, v so =0 v note : the integrated bootstrap diode does not work well with the trapezoidal control. downloaded from: http:///
irs233(0,2)(d)(s&j)pbf static electrical characteristics continued v bias (v cc , v bs1,2,3 ) = 15 v, v so1,2,3 = v ss and t a = 25 c unless otherwise specified. the v in, v th and i in parameters are referenced to v ss and are applicable to all six logic input leads: hi n1,2,3 & lin1,2,3. the v o and i o parameters are referenced to v so1,2,3 and are applicable to the respective output leads: ho1,2,3 or lo1,2,3. symbol definition min typ max units test conditions i src,amp operational amplifier output source current 7 4 v ca = 0 v, v so =1 v v cao = 4 v i snk,amp operational amplifier output sink current 1 2.1 v ca = 1 v, v so =0 v v cao = 2 v i o+,amp operational amplifier output high short circuit current 30 10 v ca = 0 v, v so =5 v v cao = 0 v i o,amp operational amplifier output low short circuit current 4 ma v ca = 5 v, v so =0 v v cao = 5 v functional block diagram note: irs2330 & irs2332 are without integrated bootstrap diode. downloaded from: http:///
irs233(0,2)(d)(s&j)pbf lead definitions symbol description hin1,2,3 logic input for highside gate driver outputs (ho1, 2,3), out of phase lin1,2,3 logic input for lowside gate driver output (lo1,2, 3), out of phase fault indicates overcurrent or undervoltage lockout (low side) has occurred, negative logic v cc lowside and logic fixed supply itrip input for overcurrent shutdown cao output of current amplifier ca negative input of current amplifier v ss logic ground v b1,2,3 highside floating supply ho1,2,3 highside gate drive output v s1,2,3 highside floating supply return lo1,2,3 lowside gate drive output v so lowside return and positive input of current ampl ifier lead assignments downloaded from: http:///
irs233(0,2)(d)(s&j)pbf application information and additional details information regarding the following topics are incl uded as subsections within this section of the data sheet. igbt/mosfet gate drive switching and timing relationships deadtime matched propagation delays input logic compatibility undervoltage lockout protection shootthrough protection fault reporting overcurrent protection overtemperature shutdown protection truth table: undervoltage lockout, itrip advanced input filter shortpulse / noise rejection integrated bootstrap functionality bootstrap power supply design separate logic and power grounds negative v s transient soa dc bus current sensing pcb layout tips integrated bootstrap fet limitation additional documentation igbt/mosfet gate drive the irs233(2,0)(d) hvics are designed to drive up t o six mosfet or igbt power devices. figures 1 and 2 illustrate several parameters associated with the gate drive functiona lity of the hvic. the output current of the hvic, used to drive the gate of the power switch, is defined as i o . the voltage that drives the gate of the external power switch is defined as v ho for the high side power switch and v lo for the lowside power switch; this parameter is s ometimes generically called v out and in this case does not differentiate between the highside or low side output voltage. v s (or com) ho (or lo) v b (or v cc ) i o+ v ho (or v lo ) + v s (or com) ho (or lo) v b (or v cc ) i o figure 1: hvic sourcing current figure 2: hvic sinking current downloaded from: http:///

irs233(0,2)(d)(s&j)pbf switching and timing relationships the relationship between the input and output signa ls of the irs233(0,2)(d) are illustrated below in f igures 3. from these figures, we can see the definitions of several timi ng parameters (i.e., pw in , pw out , t on , t off , t r , and t f ) associated with this device. linx (or hinx) 50% 50% pw in pw out 10% 10% 90% 90% t off t on t r t f lox (or hox) figure 3: switching time waveforms the following two figures illustrate the timing rel ationships of some of the functionality of the irs2 33(0,2)(d); this functionality is described in further detail later in this docume nt. during interval a of figure 4, the hvic has receive d the command to turnon both the high and lowsid e switches at the same time; as a result, the shootthrough protection of the hvic has prevented this condition and both the high and lowside output are held in the off state. interval b of figures 4 shows that the signal on th e itrip input pin has gone from a low to a high sta te; as a result, all of the gate drive outputs have been disabled (i.e., see th at hox has returned to the low state; lox is also h eld low) and a fault is reported by the fault output transitioning to the l ow state. once the itrip input has returned to the low state, the fault condition is latched until the all linx become high . downloaded from: http:///

irs233(0,2)(d)(s&j)pbf

a b figure 4: input/output timing diagram deadtime this family of hvics features integrated deadtime p rotection circuitry. the deadtime for these ics is fixed; other ics within irs hvic portfolio feature programmable deadtime f or greater design flexibility. the deadtime featur e inserts a time period (a minimum deadtime) in which both the high and lows ide power switches are held off; this is done to en sure that the power switch being turned off has fully turned off before the second power switch is turned on. this minimu m deadtime is automatically inserted whenever the external deadti me is shorter than dt; external deadtimes larger th an dt are not modified by the gate driver. figure 5 illustrates the deadt ime period and the relationship between the output gate signals. the deadtime circuitry of the irs233(0,2)(d) is mat ched with respect to the high and lowside outputs of a given channel; additionally, the deadtimes of each of the three ch annels are matched. figure 5: illustration of deadtime downloaded from: http:///

irs233(0,2)(d)(s&j)pbf matched propagation delays the irs233(0,2)(d) family of hvics is designed with propagation delay matching circuitry. with this f eature, the ics response at the output to a signal at the input req uires approximately the same time duration (i.e., t on , t off ) for both the low side channels and the highside channels. addition ally, the propagation delay for each lowside chann el is matched when compared to the other lowside channels and the pro pagation delays of the highside channels are match ed with each other. the propagation turnon delay (t on ) of the irs233(0,2)(d) is matched to the propagati on turnon delay (t off ). input logic compatibility the inputs of this ic are compatible with standard cmos and ttl outputs. the irs233(0,2)(d) family ha s been designed to be compatible with 3.3 v and 5 v logiclevel signal s. the irs233(0,2)(d) features an integrated 5.2 v zener clamp on the hin, lin, and itrip pins. figure 6 illustrates an input signal to the irs233(0,2)(d), its input thres hold values, and the logic state of the ic as a result of the input signal. figure 6: hin & lin input thresholds undervoltage lockout protection this family of ics provides undervoltage lockout pr otection on both the v cc (logic and lowside circuitry) power supply and th e v bs (highside circuitry) power supply. figure 7 is u sed to illustrate this concept; v cc (or v bs ) is plotted over time and as the waveform crosses the uvlo threshold (v ccuv+/ or v bsuv+/ ) the undervoltage protection is enabled or disable d. upon powerup, should the v cc voltage fail to reach the v ccuv+ threshold, the ic will not turnon. additionally, if the v cc voltage decreases below the v ccuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition and shutdown the high and lowside gate drive outputs, and the fault pin will transition to the low state to inform the controller of the fault condition. upon powerup, should the v bs voltage fail to reach the v bsuv threshold, the ic will not turnon. additionally, if the v bs voltage decreases below the v bsuv threshold during operation, the undervoltage locko ut circuitry will recognize a fault condition, and shutdown the highside gate drive outputs of the ic . the uvlo protection ensures that the ic drives the external power devices only when the gate supply vo ltage is sufficient to fully enhance the power devices. without this feat ure, the gates of the external power switch could b e driven with a low voltage, resulting in the power switch conducting c urrent while the channel impedance is high; this co uld result in very high conduction losses within the power device and could lead to power device failure. downloaded from: http:///

irs233(0,2)(d)(s&j)pbf figure 7: uvlo protection shootthrough protection the irs233(0,2)(d) family of highvoltage ics is eq uipped with shootthrough protection circuitry (als o known as cross conduction prevention circuitry). figure 8 shows h ow this protection circuitry prevents both the high and lowside switches from conducting at the same time. table 1 illustra tes the input/output relationship of the devices in the form of a truth table. note that the irs233(0,2)(d) has inverting inputs ( the output is outofphase with its respective inpu t). figure 8: illustration of shootthrough protection circuitry irs233(0,2)(d) hin lin ho lo 0 0 0 0 0 1 1 0 1 0 0 1 1 1 0 0 table 1: input/output truth table downloaded from: http:///

irs233(0,2)(d)(s&j)pbf fault reporting the irs233(0,2)(d) family provides an integrated fa ult reporting output. there are two situations tha t would cause the hvic to report a fault via the fault pin. the first is an undervoltage condition of v cc and the second is if the itrip pin recognizes a fault. once the fault condition occurs, the faul t pin is internally pulled to v ss and the fault condition is latched. the fault output stays in the low state until the fault condi tion has been removed by all linx set to high state . once the fault is removed, the voltage on the fault pin will return to v cc . overcurrent protection the irs233(0,2)(d) hvics are equipped with an itrip input pin. this functionality can be used to dete ct overcurrent events in the dc bus. once the hvic detects an overcurr ent event through the itrip pin, the outputs are sh utdown, a fault is reported through the fault pin. the level of current at which the overcurrent prot ection is initiated is determined by the resistor n etwork (i.e., r 0 , r 1 , and r 2 ) connected to itrip as shown in figure 9, and the it rip threshold (v it,th+ ). the circuit designer will need to determine the maximum allowable level of current in the dc bus a nd select r 0 , r 1 , and r 2 such that the voltage at node v x reaches the overcurrent threshold (v it,th+ ) at that current level. v it,th+ = r 0 i dc (r 1 /(r 1 +r 2 )) i rs233(0,2)(d) figure 9: programming the overcurrent protection for example, a typical value for resistor r 0 could be 50 m. the voltage of the itrip pin shou ld not be allowed to exceed 5 v; if necessary, an external voltage clamp may be u sed. overtemperature shutdown protection the itrip input of the irs233(0,2)(d) can also be u sed to detect overtemperature events in the system and initiate a shutdown of the hvic (and power switches) at that t ime. in order to use this functionality, the circu it designer will need to design the resistor network as shown in figure 10 a nd select the maximum allowable temperature. this network consists of a thermistor and two stand ard resistors r 3 and r 4 . as the temperature changes, the resistance of the thermistor will change; this will result in a chang e of voltage at node v x . the resistor values should be selected such the voltage v x should reach the threshold voltage (v it,th+ ) of the itrip functionality by the time that the m aximum allowable temperature is reached. the voltage of the itrip p in should not be allowed to exceed 5 v. when using both the overcurrent protection and ov ertemperature protection with the itrip input, or ing diodes (e.g., dl4148) can be used. this network is shown in figu re 11; the oring diodes have been labeled d 1 and d 2 . downloaded from: http:///

irs233(0,2)(d)(s&j)pbf figure 10: programming overtemperature protection figure 11: using overcurrent protection and overt emperature protection truth table: undervoltage lockout and itrip table 2 provides the truth table for the irs233(0,2 )(d). the first line shows that the uvlo for v cc has been tripped; the fault output has gone low and the gate drive output s have been disabled. v ccuv is not latched in this case and when v cc is greater than v ccuv , the fault output returns to the high impedance st ate. the second case shows that the uvlo for v bs has been tripped and that the highside gate drive outputs have been disabled. after v bs exceeds the v bsuv threshold , ho will stay low until the hvic input receives a new falling transition of hin. the third case shows the normal operation of the hvic. the f ourth case illustrates that the itrip trip threshol d has been reached and that the gate drive outputs have been disabled and a fault has been reported through the fault pin. th e fault output stays in the low state until the fault condition has been remove d by all linx set to high state. once the fault is removed, the voltage on the fault pin will return to v cc . vcc vbs itrip fault lo ho uvlo v cc < v ccuv 0 0 0 uvlo v bs 15 v < v bsuv 0 v high impedance lin 0 normal operation 15 v 15 v 0 v high impedance lin hin itrip fault 15 v 15 v >v itrip 0 0 0 table 2: irs233(0,2)(d) uvlo, itrip & fault truth t able advanced input filter the advanced input filter allows an improvement in the input/output pulse symmetry of the hvic and hel ps to reject noise spikes and short pulses. this input filter has bee n applied to the hin and lin. the working principle of the new filter is shown in figures 12 and 13. figure 12 shows a typical input filter and the asym metry of the input and output. the upper pair of w aveforms (example 1) show an input signal with a duration much longer th en t fil,in ; the resulting output is approximately the differe nce between the input signal and t fil,in . the lower pair of waveforms (example 2) show an input signal with a duration slightly longer then t fil,in ; the resulting output is approximately the differe nce between the input signal and t fil,in . figure 13 shows the advanced input filter and the s ymmetry between the input and output. the upper pa ir of waveforms (example 1) show an input signal with a duration mu ch longer then t fil,in ; the resulting output is approximately the same duration as the input signal. the lower pair of w aveforms (example 2) show an input signal with a du ration slightly longer then t fil,in ; the resulting output is approximately the same du ration as the input signal. downloaded from: http:///

irs233(0,2)(d)(s&j)pbf figure 12: typical input filter figure 13: advanced input filter shortpulse / noise rejection this devices input filter provides protection agai nst shortpulses (e.g., noise) on the input lines. if the duration of the input signal is less than t fil,in , the output will not change states. example 1 of figure 14 shows the input and output in the low sta te with positive noise spikes of durations less than t fil,in ; the output does not change states. example 2 of figure 19 shows the input and output in the high state with negative no ise spikes of durations less than t fil,in ; the output does not change states. example 1 example 2 figure 14: noise rejecting input filters figures 15 and 16 present lab data that illustrates the characteristics of the input filters while rec eiving on and off pulses. the input filter characteristic is shown in figure 15; the left side illustrates the narrow pulse on ( short positive pulse) characteristic while the left shows the narrow puls e off (short negative pulse) characteristic. the x axis of figure 20 shows the duration of pw in , while the yaxis shows the resulting pw out duration. it can be seen that for a pw in duration less than t fil,in , that the resulting pw out duration is zero (e.g., the filter rejects the inp ut signal/noise). we also see that once the pw in duration exceed t fil,in , that the pw out durations mimic the pw in durations very well over this interval with the sy mmetry improving as the duration increases. to ensure pro per operation of the hvic, it is suggested that the input pulse width for the highside inputs be 500 ns. the difference between the pw out and pw in signals of both the narrow on and narrow off cases is shown in figure 16; the careful reader will note the scale of the yaxis. the xaxis of figure 21 shows the duration of pw in , while the yaxis shows the resulting pw out Cpw in duration. this data illustrates the performance a nd near symmetry of this input filter. downloaded from: http:///

irs233(0,2)(d)(s&j)pbf time (ns) figure 15: irs233(0,2)(d) input filter characterist ic figure 16: difference between the input pulse and t he output pulse integrated bootstrap functionality the new irs233(0,2)d family features integrated hig hvoltage bootstrap mosfets that eliminate the need of the external bootstrap diodes and resistors in many applications . there is one bootstrap mosfet for each highside ou tput channel and it is connected between the v cc supply and its respective floating supply (i.e., v b1 , v b2 , v b3 ); see figure 17 for an illustration of this intern al connection. the integrated bootstrap mosfet is turned on only d uring the time when lo is high, and it has a limi ted source current due to r bs . the v bs voltage will be charged each cycle depending on th e ontime of lo and the value of the c bs capacitor, the drainsource (collectoremitter) drop of the extern al igbt (or mosfet), and the lowside freewheeling diode drop. the bootstrap mosfet of each channel follows the st ate of the respective lowside output stage (i.e., the bootstrap mosfet is on when lo is high, it is off when lo is low), u nless the v b voltage is higher than approximately 110% of v cc . in that case, the bootstrap mosfet is designed to remain of f until v b returns below that threshold; this concept is illu strated in figure 18. downloaded from: http:///

irs233(0,2)(d)(s&j)pbf v cc v b1 v b2 v b3 figure 17: internal bootstrap mosfet connection fig ure 18: bootstrap mosfet state diagram a bootstrap mosfet is suitable for most of the pwm modulation schemes and can be used either in parall el with the external bootstrap network (i.e., diode and resistor) or as a replacement of it. the use of the integrated boo tstrap as a replacement of the external bootstrap network may have some limita tions. an example of this limitation may arise when this functionality is used in noncomplementary pwm schemes (typically 6 step modulations) and at very high pwm duty cycle. in these cases, superior performances can be achieved by using an e xternal bootstrap diode in parallel with the intern al bootstrap network. bootstrap power supply design for information related to the design of the bootst rap power supply while using the integrated bootstr ap functionality of the irs233(0,2)d family, please refer to application no te 1123 (an1123) entitled bootstrap network analy sis: focusing on the integrated bootstrap functionality. this applicat ion note is available at www.irf.com . for information related to the design of a standard bootstrap power supply (i.e., using an external di screte diode) please refer to design tip 044 (dt044) entitled using monolit hic high voltage gate drivers. this design tip is available at www.irf.com . separate logic and power grounds the irs233(0,2)(d) has separate logic and power gro und pin (v ss and vso respectively) to eliminate some of the noi se problems that can occur in power conversion applica tions. current sensing shunts are commonly used in many applications for power inverter protection (i.e., overcurrent p rotection), and in the case of motor drive applicat ions, for motor current measurements. in these situations, it is often ben eficial to separate the logic and power grounds. figure 19 shows a hvic with separate v ss and vso pins and how these two grounds are used in the system. the v ss is used as the reference point for the logic and over current circuitry; v x in the figure is the voltage between the itrip pin and the v ss pin. alternatively, the vso pin is the reference point for the lowside gate drive circuitry. the o utput voltage used to drive the lowside gate is v lo vso; the gateemitter voltage (v ge ) of the lowside switch is the output voltage of t he driver minus the drop across r g,lo . downloaded from: http:///

irs233(0,2)(d)(s&j)pbf v s (x3) hvic ho (x3) v b (x3) lo (x3) com dc+ bus dc bus v cc d bs c bs v ss r g,lo r g,ho v s1 v s2 v s3 r 1 r 2 r 0 v ge1 + v ge2 + v ge3 + itrip v x + figure 19: separate v ss and vso pins negative v s transient soa a common problem in todays highpower switching co nverters is the transient response of the switch no des voltage as the power switches transition on and off quickly while carrying a large current. a typical 3phase invert er circuit is shown in figure 20; here we define the power switches and diodes of the inverter. if the highside switch (e.g., the igbt q1 in figur es 21 and 22) switches off, while the u phase curre nt is flowing to an inductive load, a current commutation occurs from h ighside switch (q1) to the diode (d2) in parallel with the lowside switch of the same inverter leg. at the same instance, th e voltage node v s1 , swings from the positive dc bus voltage to the ne gative dc bus voltage. figure 20: three phase inverter downloaded from: http:///
irs233(0,2)(d)(s&j)pbf q1 on d2 v s1 q2 off i u dc+ bus dc bus figure 21: q1 conducting figure 22: d2 conducting also when the v phase current flows from the induct ive load back to the inverter (see figures 23 and 2 4), and q4 igbt switches on, the current commutation occurs from d3 to q4. at the same instance, the voltage node, v s2 , swings from the positive dc bus voltage to the negative dc bus volt age. figure 23: d3 conducting figure 24: q4 conducting however, in a real inverter circuit, the v s voltage swing does not stop at the level of the ne gative dc bus, rather it swings below the level of the negative dc bus. this unders hoot voltage is called negative v s transient. the circuit shown in figure 25 depicts one leg of t he three phase inverter; figures 26 and 27 show a s implified illustration of the commutation of the current between q1 and d2. t he parasitic inductances in the power circuit from the die bonding to the pcb tracks are lumped together in l c and l e for each igbt. when the highside switch is on, v s1 is below the dc+ voltage by the voltage drops associated with the power swit ch and the parasitic elements of the circuit. when the highside power switch turns off, the load current momentarily flow s in the lowside freewheeling diode due to the ind uctive load connected to v s1 (the load is not shown in these figures). this cu rrent flows from the dc bus (which is connected to the vso pin of the hvic) to the load and a negative voltage between v s1 and the dc bus is induced (i.e., the vso pin of t he hvic is at a higher potential than the v s pin). downloaded from: http:///

irs233(0,2)(d)(s&j)pbf figure 25: parasitic elements figure 26: v s positive figure 27: v s negative in a typical motor drive system, dv/dt is typically designed to be in the range of 35 v/ns. the negat ive v s transient voltage can exceed this range during some events such as sh ort circuit and overcurrent shutdown, when di/dt i s greater than in normal operation. international rectifiers hvics have been designed for the robustness required in many of todays dema nding applications. an indication of the irs233(0,2)(d)s robustness can b e seen in figure 28, where there is represented the irs233(0,2)(d) safe operating area at v bs =15v based on repetitive negative v s spikes. a negative v s transient voltage falling in the grey area (outside soa) may lead to ic permanent damage; vice versa unwanted functional anomalies or permanent da mage to the ic do not appear if negative vs transients fall inside soa. at v bs =15v in case of v s transients greater than 16.5 v for a period of ti me greater than 50 ns; the hvic will hold by design the highside outputs in the off state for 4.5 s. figure 28: negative v s transient soa for irs233(0,2)(d) even though the irs233(0,2)(d) has been shown able to handle these large negative v s transient conditions, it is highly recommended that the circuit designer always limit the negative v s transients as much as possible by careful pcb layo ut and component use. downloaded from: http:///
irs233(0,2)(d)(s&j)pbf dc bus current sensing a ground referenced current signal amplifier has be en included so that the current in the return leg o f the dc bus may be monitored. a typical circuit configuration is provi ded in fig.29. the signal coming from the shunt res istor is amplified by the ratio (r1+r2)/r2. additional details can be found o n design tip dt 926. this design tip is available at www.irf.com . figure 29: current amplifier typical configuration in the following figures 30, 31, 32, 33 the configu rations used to measure the operational amplifier c haracteristics are shown. !! ! " !# "" 15 v 50 pf
90% 10% 1v 0v t1 t2 v t1 v sr + t2 v sr !! ! " ! # "" 15v + 1k 20 k 0.2v " " 21 0.2v figure 30: operational amplifier slew rate measurem ent figure 31: operational amplifier input offset v oltage measurement downloaded from: http:///
irs233(0,2)(d)(s&j)pbf !! ! " ! # "" 15v $%&'(% !
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cmrr = 20 * log (v cao1 C 0.1v) C(v cao 2 C1.1v) 1v (db) figure 32: operational amplifier common mode reject ion measurement figure 33: operational amplifier power supply rejec tion measurement pcb layout tips distance between high and low voltage components: its strongly recommended to place the components tied to the floating voltage pins (v b and v s ) near the respective high voltage portions of the device. the irs233(0,2)(d) in the plcc44 package has had some unused pins removed in order to maximi ze the distance between the high voltage and low vo ltage pins. please see the case outline plcc44 information in t his datasheet for the details. ground plane: in order to minimize noise coupling, the ground pl ane should not be placed under or near the high vol tage floating side. gate drive loops: current loops behave like antennas and are able to receive and transmit em noise (see figure 34). in order to reduce the em coupling and improve the power swi tch turn on/off performance, the gate drive loops m ust be reduced as much as possible. moreover, current can be injected inside the gate drive loop via the igbt collector togate parasitic capacitance. the parasitic autoinductance of the g ate loop contributes to developing a voltage across the gateemitter, thus increasing the possibility of a self turnon effect . figure 34: antenna loops downloaded from: http:///
irs233(0,2)(d)(s&j)pbf supply capacitor: it is recommended to place a bypass capacitor (c in ) between the v cc and v ss pins. this connection is shown in figure 35. a ceramic 1 f ceramic capacit or is suitable for most applications. this compone nt should be placed as close as possible to the pins in order to reduce pa rasitic elements. i rs233(0,2)(d) figure 35: supply capacitor routing and placement : power stage pcb parasitic elements can contribute to large negative voltage transients at the switch node; it is recommended to limit the phase voltage negative transients. in order to avoid such condit ions, it is recommended to 1) minimize the highside emitter to lowside co llector distance, and 2) minimize the lowside emit ter to negative bus rail stray inductance. however, where negative v s spikes remain excessive, further steps may be take n to reduce the spike. this includes placing a resistor (5 or less) between t he v s pin and the switch node (see figure 36), and in so me cases using a clamping diode between v ss and v s (see figure 37). see dt044 at www.irf.com for more detailed information. figure 36: v s resistor figure 37: v s clamping diode downloaded from: http:///
irs233(0,2)(d)(s&j)pbf integrated bootstrap fet limitation the integrated bootstrap fet functionality has an o perational limitation under the following bias cond itions applied to the hvic: vcc pin voltage = 0v and vs or vb pin voltage > 0 in the absence of a vcc bias, the integrated bootst rap fet voltage blocking capability is compromised and a current conduction path is created between vcc & vb pins, a s illustrated in fig.38 below, resulting in power l oss and possible damage to the hvic. figure 38: current conduction path between vcc and vb pin relevant application situations: the above mentioned bias condition may be encounter ed under the following situations: in a motor control application, a permanent magnet motor naturally rotating while vcc power is off. i n this condition, back emf is generated at a motor termina l which causes high voltage bias on vs nodes result ing unwanted current flow to vcc. potential situations in other applications where v s/vb node voltage potential increases before the vc c voltage is available (for example due to sequencing delays in smps supplying vcc bias) application workaround: insertion of a standard pn junction diode between vcc pin of ic and positive terminal of vcc capacito rs (as illustrated in fig.39) prevents current conduction outof vcc pi n of gate driver ic. it is important not to connect the vcc capacitor directly to pin of ic. diode selection is based on 25v rating or above & current capability aligned to icc consumption of ic 100ma should cover most application situations. a s an example, part number # ll4154 from diodes inc (25v/150ma standard diode) can be used. downloaded from: http:///
irs233(0,2)(d)(s&j)pbf figure 39: diode insertion between vcc pin and vcc capacitor note that the forward voltage drop on the diode ( ) must be taken into account when biasing the vcc p in of the ic to meet uvlo requirements.
. additional documentation several technical documents related to the use of h vics are available at www.irf.com ; use the site search function and the document number to quickly locate them. below is a short list of some of these documents. dt973: managing transients in control ic driven po wer stages an1123: bootstrap network analysis: focusing on th e integrated bootstrap functionality dt044: using monolithic high voltage gate drivers an978: hv floating mosgate driver ics vcc vss (or com) vb vcc capacitor vcc vss (or com) vb vcc capacitor downloaded from: http:///
irs233(0,2)(d)(s&j)pbf parameter temperature trends figures 4078 provide information on the experiment al performance of the irs233(0,2)(d)(s&j) hvic. th e line plotted in each figure is generated from actual lab data. a small n umber of individual samples were tested at three te mperatures (40 oc, 25 oc, and 125 oc) in order to generate the experimental ( exp.) curve. the line labeled exp. consist of thre e data points (one data point at each of the tested temperatures) that have been connected together to illustrate the understood tem perature trend. the individual data points on the curve were determined by calculating the averaged experimental value of the parameter (for a given temperature). 0 100 200 300 400 500 600 700 800 50 25 0 25 50 75 100 125 temperature ( o c) t on (ns) exp. fig. 40. turnon propagation delay vs. temperature 0 100 200 300 400 500 600 700 800 50 25 0 25 50 75 100 125 temperature ( o c) t on (ns) exp. fig. 41. turnon propagation delay vs. temperature 0 100 200 300 400 500 600 700 800 50 25 0 25 50 75 100 125 temperature ( o c) t off (ns) exp. fig. 42. turnoff propagation delay vs. temperature 0 100 200 300 400 500 600 700 800 50 25 0 25 50 75 100 125 temperature ( o c) t off (ns) exp. fig. 43. turnoff propagation delay vs. temperature downloaded from: http:///
irs233(0,2)(d)(s&j)pbf 0 20 40 60 80 100 120 140 160 180 200 50 25 0 25 50 75 100 125 temperature ( o c) t r (ns) exp. fig. 44. turnon rise time vs. temperature 0 10 20 30 40 50 60 50 25 0 25 50 75 100 125 temperature ( o c) t f (ns) exp. fig.45. turnoff fall time vs. temperature 0 100 200 300 400 500 600 700 800 900 1000 50 25 0 25 50 75 100 125 temperature ( o c) t itrip (ns) exp. fig. 46. itrip to output shutdown propagation delay vs. temperature 0 100 200 300 400 500 600 700 800 900 1000 50 25 0 25 50 75 100 125 temperature ( o c) t flt (ns) exp. fig. 47. itrip to fault indication delay vs. temperature 0 2000 4000 6000 8000 10000 12000 14000 16000 50 25 0 25 50 75 100 125 temperature ( o c) tfltclr (ns) exp. fig.48. fault clear time vs. temperature 0 200 400 600 800 1000 1200 50 25 0 25 50 75 100 125 temperature ( o c) dlton1 (ns) exp. fig. 49. dead time vs. temperature downloaded from: http:///
irs233(0,2)(d)(s&j)pbf 0 10 20 30 40 50 60 50 25 0 25 50 75 100 125 temperature ( o c) sr+_amp (v/us) exp. fig. 50. operational amplifier slew rate (+) vs. temperature 0 1 2 3 4 5 6 50 25 0 25 50 75 100 125 temperature ( o c) sr_amp (v/us) exp. fig. 51. operational amplifier slew rate () vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 50 25 0 25 50 75 100 125 temperature ( o c) lin1_vth+ (v) exp. fig. 52. input positive going threshold vs. temperature 0.0 0.5 1.0 1.5 2.0 2.5 50 25 0 25 50 75 100 125 temperature ( o c) lin1_vth (v) exp. fig. 53. input negative going threshold vs. temperature 0 100 200 300 400 500 600 700 800 50 25 0 25 50 75 100 125 temperature ( o c) v it,th+ (mv) exp. p. fig. 54. itrip input positive going threshold vs. temperature 0 100 200 300 400 500 600 700 800 50 25 0 25 50 75 100 125 temperature ( o c) v it,th (mv) exp. fig. 55. itrip input negative going threshold vs. temperature downloaded from: http:///
irs233(0,2)(d)(s&j)pbf 0 50 100 150 200 250 300 350 400 450 50 25 0 25 50 75 100 125 temperature ( o c) vol_lo1 (mv) exp. fig. 56. low level output voltage vs. temperature 0 10 20 30 40 50 60 50 25 0 25 50 75 100 125 temperature ( o c) ileak1_vccmax (a) exp. fig. 57. offset supply leakage current vs. temperature 0 2 4 6 8 10 12 50 25 0 25 50 75 100 125 temperature ( o c) i qcc1 (ma) exp. fig. 58. quiescent v cc supply current vs. temperature 0 1 2 3 4 5 6 7 50 25 0 25 50 75 100 125 temperature ( o c) i qcc0 (ma) exp. fig. 59. quiescent v cc supply current vs. temperature 0 10 20 30 40 50 60 70 80 50 25 0 25 50 75 100 125 temperature ( o c) i qbs10 (a) exp. fig. 60. quiescent v bs supply current vs. temperature 0 10 20 30 40 50 60 70 80 50 25 0 25 50 75 100 125 temperature ( o c) i qbs11 (a) exp. fig. 61. quiescent v bs supply current vs. temperature downloaded from: http:///

irs233(0,2)(d)(s&j)pbf 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.6 50 25 0 25 50 75 100 125 temperature ( o c) v ccuv (v) exp. fig. 62. v cc supply undervoltage negative going threshold vs. temperature 8.2 8.4 8.6 8.8 9.0 9.2 9.4 9.6 9.8 50 25 0 25 50 75 100 125 temperature ( o c) v ccuv+ (v) exp. fig. 63. v cc supply undervoltage positive going threshold vs. temperature 6.0 6.5 7.0 7.5 8.0 8.5 9.0 50 25 0 25 50 75 100 125 temperature ( o c) v bsuv (v) exp. fig. 64. v bs supply undervoltage negative going threshold vs. temperature 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 50 25 0 25 50 75 100 125 temperature ( o c) v bsuv+ (v) exp. fig. 65. v bs supply undervoltage positive going threshold vs. temperature 0 10 20 30 40 50 60 70 80 90 50 25 0 25 50 75 100 125 temperature ( o c) r on,flt () exp. fig. 66. fault low onresistance vs. temperature 450 400 350 300 250 200 150 100 50 0 50 25 0 25 50 75 100 125 temperature ( o c) i o+ (ma) exp. p. fig. 67. output high short circuit pulsed current vs. temperature downloaded from: http:///
irs233(0,2)(d)(s&j)pbf 6 106 206 306 406 506 606 706 50 25 0 25 50 75 100 125 temperature ( o c) i o (ma) exp. fig. 68. output low short circuit pulsed current vs. temperature 20 15 10 5 0 5 10 15 20 50 25 0 25 50 75 100 125 temperature ( o c) vos_amp (mv) exp. p. fig. 69. offset opamp vs. temperature 0 20 40 60 80 100 120 140 160 180 200 50 25 0 25 50 75 100 125 temperature ( o c) psrr_amp (db) exp. fig. 70. operational amplifier power supply rejection ratio vs. temperature 0 20 40 60 80 100 120 140 160 180 200 50 25 0 25 50 75 100 125 temperature ( o c) cmrr_amp (db) exp. fig. 71. operational amplifier common mode rejection ratio vs. temperature 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 50 25 0 25 50 75 100 125 temperature ( o c) voh_amp (v) exp. fig. 72. operational amplifier high level output voltage vs. temperature 0 5 10 15 20 25 30 35 50 25 0 25 50 75 100 125 temperature ( o c) voh_amp (mv) exp. fig. 73. operational amplifier low level output voltage vs. temperature downloaded from: http:///
irs233(0,2)(d)(s&j)pbf 0 1 2 3 4 5 6 50 25 0 25 50 75 100 125 temperature ( o c) isnk_amp (ma) exp. fig. 74. operational amplifier output sink current vs. temperature 0 2 4 6 8 10 12 14 16 50 25 0 25 50 75 100 125 temperature ( o c) io_amp (ma) exp. fig. 75. operational amplifier output low short circuit current vs. temperature 16 14 12 10 8 6 4 2 0 50 25 0 25 50 75 100 125 temperature ( o c) isrc_amp (ma) exp. fig. 76. operational amplifier output source current vs. temperature 35 30 25 20 15 10 5 0 50 25 0 25 50 75 100 125 temperature ( o c) io+_amp (ma) exp. fig. 77. operational amplifier output high short circuit current vs. temperature 14 12 10 8 6 4 2 0 50 25 0 25 50 75 100 125 temperature ( o c) vs1_rst_domin (v) exp. fig. 78. max Cvs vs. temperature downloaded from: http:///
irs233(0,2)(d)(s&j)pbf case outlines downloaded from: http:///
irs233(0,2)(d)(s&j)pbf case outlines downloaded from: http:///
irs233(0,2)(d)(s&j)pbf tape and reel details: soic28w carrier tape dimension for 28soicw code min max min max a 11.90 12.10 0.468 0.476 b 3.90 4.10 0.153 0.161 c 23.70 24.30 0.933 0.956 d 11.40 11.60 0.448 0.456 e 10.80 11.00 0.425 0.433 f 18.20 18.40 0.716 0.724 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 28soicw code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 30.40 n/a 1.196 g 26.50 29.10 1.04 1.145 h 24.40 26.40 0.96 1.039 metric imperial + ! , - . +/!- ,$ +"$ $ ,+,+++,,+! a h f e g d b c downloaded from: http:///
irs233(0,2)(d)(s&j)pbf tape and reel details: plcc44 carrier tape dimension for 44plcc code min max min max a 23.90 24.10 0.94 0.948 b 3.90 4.10 0.153 0.161 c 31.70 32.30 1.248 1.271 d 14.10 14.30 0.555 0.562 e 17.90 18.10 0.704 0.712 f 17.90 18.10 0.704 0.712 g 2.00 n/a 0.078 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 44plcc code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 38.4 n/a 1.511 g 34.7 35.8 1.366 1.409 h 32.6 33.1 1.283 1.303 metric imperial + ! , - . +/!- ,$ +"$ $ ,+,+++,,+! a h f e g d b c downloaded from: http:///
irs233(0,2)(d)(s&j)pbf ordering information standard pack base part number package type form quantity complete part number tube/bulk 25 irs233(0,2)(d)spbf soic28w tape and reel 1000 irs233(0,2)(d)strpbf tube/bulk 27 irs233(0,2)(d)jpbf irs233(0,2)(d) plcc44 tape and reel 500 irs233(0,2)(d)jtrpbf the information provided in this document is believ ed to be accurate and reliable. however, internatio nal rectifier assumes no responsibility for the consequences of the use of this information . international rectifier assumes no responsibilit y for any infringement of patents or of other rights of third parties which may result from the u se of this information. no license is granted by i mplication or otherwise under any patent or patent rights of international rectifier. the spec ifications mentioned in this document are subject t o change without notice. this document supersedes and replaces all information previously supplied. for technical support, please contact irs technica l assistance center http://www.irf.com/technicalinfo/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 2527105 downloaded from: http:///
irs233(0,2)(d)(s&j)pbf change history revision date change comments 0.0 10/17/07 initial data sheet converted from irs2 130xd data sheet 0.1 03/05/08 initial review 0.2 03/18/08 included tritemp plots 0.3 03/18/08 updated test conditions 0.4 03/26/08 updated limits using dr3 limits table 0.5 03/27/08 included application notes 0.6 03/27/08 updated minor errors and completed rev iew for dr3 0.7 03/28/08 corrected reflow temperature for plcc44 to 245 c 0.8 04/02/08 added integrated operational amplifier feature on front page and rohs compliant. 0.9 04/11/08 corrected logic level compatible on pa ge1 from 2.5v to 3.3v 1.0 04/15/08 added mdt parameter 1.1 04/16/08 updated mdt spec. and changed latchup level to a 1.2 04/28/08 removed typical mdt spec.; mdt expecte d to be zero and cannot be more than maximum spec. may 8, 08 changed file format from rev1.2 to may 8, 2008. corrected part number in fig. 15 july 8, 08 changed iqcc test condition to vin=4v f rom 0v. june 1, 11 add bootstrap fet limitation downloaded from: http:///

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